/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

`include "defines.v"

module mem_wb(
	input wire	clk,
	input wire	rst,
	input wire[5:0]	stall,

	// source from execute info
	input wire[`RegAddrBus]		mem_wd,
	input wire			mem_wreg,
	input wire[`RegBus]		mem_wdata,

	// sink to mem info
	output reg[`RegAddrBus]		wb_wd,
	output reg			wb_wreg,
	output reg[`RegBus]		wb_wdata
);

	always @ (posedge clk) begin
		if (rst == `RstEnable) begin
			wb_wd	 <= `NOPRegAddr;
			wb_wreg <= `WriteDisable;
			wb_wdata <= `ZeroWord;
		end else if (stall[4] == `Stop && stall[5] == `NoStop) begin
			wb_wd	 <= `NOPRegAddr;
			wb_wreg	 <= `WriteDisable;
			wb_wdata <= `ZeroWord;
		end else if (stall[4] == `NoStop) begin
			wb_wd	 <= mem_wd;
			wb_wreg <= mem_wreg;
			wb_wdata <= mem_wdata;	
		end
	end

endmodule
